In static random access memory (SRAM), for a faster read access time in a read mode, the internal ground node of the memory cell in some approaches is set at the conventional ground or voltage VSS, and the internal supply node is set at the conventional operation voltage VDD. In a data retention mode (e.g., after a reading mode), to reduce current leakages, either the internal ground node is raised by a voltage, e.g., voltage Vred, or the internal supply node is lowered, e.g., by voltage Vred. In some approaches that use a self-bias diode, raising the internal ground node from voltage VSS by voltage Vred depends on the current driving capabilities of the memory cell and can take a long time, which negates the advantages of the power saved in the data retention scheme. To fix the problem, an extra circuit (e.g., a large driver) can be used to quickly pull up voltage VSS, but requires additional power (e.g., a large current) and generates a large amount of noise.
Like reference symbols in the various drawings indicate like elements.